1. Field of the Invention
This invention generally relates to a data output buffer circuit for a semiconductor integrated circuit, and in particular, it relates to a data output buffer circuit suitable for semiconductor memories wherein high access speed is required.
2. Description of the Prior Art
This application is related to commonly assigned Ser. No. 023,577 entitled "Buffer Circuit" filed Mar. 9, 1987. This application is also related to a commonly assigned application entitled "Semiconductor Integrated Circuit Having a Data Output Buffer Circuit" filed concurrently herewith and assigned Ser. No. 167,082.
When data is output from semiconductor integrated circuits such as semiconductor memories, the output load must be charged and discharged at high speed. During this charging and discharging, potential fluctuations, i.e. noise, are generated in the power source voltage and the reference voltage respectively. When low-level data is output in a typical semiconductor integrated circuit (discharging of output load), the potential fluctuations generated in the reference voltage are at least equal to, and usually greater than, the potential fluctuations generated in the power source voltage when high-level data is output (charging of output load). Such fluctuations or noise during these operations are a factor which may cause a malfunction of the semiconductor integrated circuit. The major part of the potential fluctuations generated in the reference voltage during the sudden discharge of the output load consists of the product L.di/dt where di/dt is the rate of increase with time of discharge current to the reference voltage and L is the parasitic inductive component on the discharge path. Since the discharge of the output load occurs rapidly, this product may take on large values, increasing the danger of circuit malfunction.
FIG. 1 is the circuit diagram of a conventional data output circuit for a semiconductor integrated circuit such as a semiconductor memory. In the Figure, the area enclosed by broken lines contains the semiconductor circuit components and the associated output buffer. These semiconductor circuit components may include memory cells, address circuitry, sensing amplifiers, and circuitry for driving the output buffers. It is generally understood that output buffers do not comprise a portion of the internal semiconductor components. This convention will be observed in what follows, i.e., the output buffer is considered distinct from the internal semiconductor circuit components. T1 is a data output terminal. T2 is a power source terminal supplied with power source voltage V.sub.DD. T3 is a reference terminal supplied with reference voltage V.sub.SS. I/O and I/O are internal data buses. Transistor 11 is a data output buffer for high-level output and transistor 12 is a data output buffer for low-level output. AND gates 13 and 14 control the respective data outputs and comprise circuitry for driving the output buffers. Parasitic resistive components 15 and 16 are present in the power source wirings. D.C. power source 17 feeds power source voltage V.sub. DD to the integrated circuit. Capacitance 18 stabilizes D.C. power source 17. Load capacitance 19 is driven by the output data of the integrated circuit. Resistive components 20, 21, 22 and inductive components 23, 24, 25 are present in the respective wirings of the external part of the integrated circuit.
When such a data output circuit outputs low-level data, internal data bus I/O becomes level "0", and I/O becomes level "1". Subsequently, the internal control signal .phi..sub.out rises to level "1", causing the output signal of AND gate 14 to become level "1". As a result, transistor 12 for low-level output, whose source-drain path is inserted between data output terminal T1 and reference terminal T3, is turned on and conducts. Thus, load capacitance 19 discharges to level "0" through terminal T1. The waveforms of the various signals in this series of operations are shown by the continuous lines in the waveform plot of FIG. 2(a). Signal N in FIG. 2(a) is the output signal of AND gate 14. When the load capacitance 19 is discharged, a large discharge current I.sub.d is generated through transistor 12, and potential fluctuations commonly called overshoot, as described above, occur on the reference voltage side due to resistive components 20, 16, 22 and inductive components 23, 25 present on the current path. When such fluctuations occur on the ground voltage side (V.sub.SS side), similar fluctuations also occur on the power source voltage side (V.sub.DD side). These potential fluctuations are shown by the continuous lines in the wave form plot of FIG. 2(b). Such fluctuations are particularly severe in an integrated circuit having a plurality of data output terminals when a low-level data is output from all terminals. Thus, the possibility of circuit component malfunction becomes very high. Conventionally, however, as shown in FIG. 1, only one low-level output transistor is provided for a single data output terminal. In these circumstances, the only option available for controlling the generation of the overshoot is to greatly restrict the current drive capacity of transistor 12, either by decreasing its channel width W, or by slowing down the rate of increase of its gate drive signal. The fluctuations of the reference and power source potentials in response to these methods are indicated by the broken line in FIG. 2(b). However, as shown by the broken lines in FIG. 2(a), if the rate of increase of the gate drive signal N of transistor 12 is too slow, the change in the signal waveform of terminal T1 is delayed, impairing the high-speed characteristics of the semiconductor memory. A similar effect occurs if the channel width W of transistor 12 is reduced. Thus the conventional circuit is subject to the drawback that the attempts to prevent malfunction by reducing potential fluctuations in the power source have resulted in increased access time.